Trench patterning with block first sidewall image transfer

ABSTRACT

A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.

CROSS REFERENCE

The present application is a divisional of and claims priority under 35U.S.C. §120 of U.S. patent application Ser. No. 13/866,293, filed onApr. 19, 2013, which is incorporated by reference in its entirety.

BACKGROUND

The present invention generally relates to semiconductor devicemanufacturing, and more particularly to trench patterning using a blockfirst sidewall image transfer technique.

Semiconductor device manufacturing generally includes various stepsincluding a patterning process. For example, the manufacturing of asemiconductor chip may start with, for example, CAD (computer aideddesign) generated device patterns and may continue with the effort toreplicate these device patterns in a substrate in which semiconductordevices can be formed. The replication process may involve the use of aphotolithography process in which a layer of photo-resist material maybe first applied on top of a substrate, and then be selectively exposedaccording to a pre-determined device pattern. Portions of thephoto-resist that are exposed to light or other ionizing radiation(e.g., ultraviolet, electron beams, X-rays, etc.) may experience somechanges in their solubility to a certain solution. Next, thephoto-resist may be developed in a developer solution, thereby removingthe non-irradiated (in a negative resist) or irradiated (in a positiveresist) portions of the resist layer, to create a photo-resist pattern.The photo-resist pattern may subsequently be copied or transferred tothe substrate underneath the photo-resist pattern.

Engineers are continuously facing the challenge of how to meet themarket demand for ever increasing device density. One technique fortight pitch patterning is to achieve twice the pattern density through atechnique called sidewall image transfer (SIT), also known as sidewallspacer image transfer. A conventional block last SIT process can includelithographically forming a mandrel above a substrate from a suitablephoto-resist material. A material suitable for forming spacers issubsequently deposited on top of the mandrel and to eventually formspacers next to the mandrels. The mandrel can then be removed and theremaining spacers can defined the desired device pattern. Next, a blockmask litho step may be applied to remove a portion of the device patternformed by the spacers. The block mask litho step may be designed todefine a pattern region of the structure, and thus ensure only a portionof the device pattern within the pattern region is transferred tounderlying layers and eventually the substrate. Lastly, the devicepattern may be transferred into an underlying substrate, again, onlywithin the pattern region defined by the block mask litho step.

However, concerns and issues have been observed in the above block lastSIT process. Accordingly it may be advantageous to make changes to thecurrent fabrication techniques to address the deficiencies describedabove.

SUMMARY

According to one embodiment of the present invention, a method isprovided. The method may include forming a tetra-layer hardmask above asubstrate, the tetra-layer hardmask including a second hardmask layerabove a first hardmask layer, removing a portion of the second hardmasklayer of the tetra-layer hardmask within a pattern region of a structureincluding the substrate and the tetra-layer hardmask, forming a set ofsidewall spacers above the tetra-layer hardmask to define a devicepattern, and transferring a portion of the device pattern into thesubstrate and within the pattern region of the structure.

According to another exemplary embodiment of the present invention, amethod is provided. The method may include forming a tetra-layerhardmask including a second hardmask layer above a first hardmask layer,defining a pattern region in the second hardmask layer, forming a devicepattern above the tetra-layer hardmask, and transferring the devicepattern to a substrate below the tetra-layer hardmask, where the devicepattern is transferred to the substrate only in the pattern regiondefined by the second hardmask layer.

According to another exemplary embodiment of the present invention, amethod is provided. The method may include forming a tetra-layerhardmask above a substrate, the tetra-layer hardmask including a firstpatterning layer, a first hardmask layer, a second patterning layer, anda second hardmask layer all of which are formed one top of one anotherand in sequence, forming a block pattern from a photo-resist materialabove the tetra-layer hardmask, and transferring the block pattern fromthe photo-resist material to the second hardmask layer, where the blockpattern in the second hardmask layer defines a pattern region. Themethod may further include forming a device pattern using a set ofsidewall spacers above the second hardmask layer, transferring thedevice pattern into the first hardmask layer, only within the patternregion, and transferring the device pattern into the substrate, onlywithin the pattern region.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a structure at an intermediate stepof fabrication in which the formation of a block pattern is illustratedaccording to an exemplary embodiment.

FIG. 2 illustrates transferring the block pattern into a block ARC layerand a block planarization layer according to an exemplary embodiment.

FIG. 3 illustrates transferring the block pattern into second hardmasklayer of a tetra-layer hardmask according to an exemplary embodiment.

FIG. 4 illustrates the formation of a mandrel above a mandrel ARC layeraccording to an exemplary embodiment.

FIG. 5 illustrates the formation of a dielectric layer above the mandreland the mandrel ARC layer according to an exemplary embodiment.

FIG. 6 illustrates a first device pattern and a second device patternformed from sidewall spacers according to an exemplary embodiment.

FIG. 7 illustrates transferring the first and second device patterns tothe mandrel ARC layer and a mandrel planarization layer according to anexemplary embodiment.

FIG. 8 illustrates transferring the first and second device patternsfrom the mandrel ARC layer and the mandrel planarization layer to asecond patterning layer according to an exemplary embodiment.

FIG. 9 illustrates transferring the first and second device patternsfrom the second patterning layer to a first hardmask layer according toan exemplary embodiment.

FIG. 10 illustrates transferring the first and second device patternsfrom the first hardmask layer to a substrate according to an exemplaryembodiment.

FIG. 11 illustrates a final structure according to an exemplaryembodiment.

The drawings are not necessarily to scale. The drawings are merelyschematic representations, not intended to portray specific parametersof the invention. The drawings are intended to depict only typicalembodiments of the invention. In the drawings, like numbering representslike elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosedherein; however, it can be understood that the disclosed embodiments aremerely illustrative of the claimed structures and methods that may beembodied in various forms. This invention may, however, be embodied inmany different forms and should not be construed as limited to theexemplary embodiments set forth herein. Rather, these exemplaryembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the scope of this invention to thoseskilled in the art. In the description, details of well-known featuresand techniques may be omitted to avoid unnecessarily obscuring thepresented embodiments.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

Current block last sidewall image transfer (SIT) techniques describedabove may have drawbacks including, for example, a limited processwindow in which the spacer height must be high or thick enough tofunction as an etch mask in one sense while at the same time shortenough to ultimately be sacrificially removed before being transferredinto underlying layers in a subsequent step. Also, the block last SITtechnique can produce a segmented or hollow alignment mark which may beused for alignment during subsequent processing steps. The segmented orhollow alignment marks offer poor contrast making alignment for futureprocessing difficult. The present invention generally relates to trenchpatterning using a block first SIT technique which may address one ormore of the deficiencies described above.

Referring now to FIGS. 1-11, exemplary process steps of forming astructure 100 in accordance with one embodiment of the present inventionare shown, and will now be described in greater detail below. Thestructure 100 can include a device pattern. Some non-limiting examplesof the device pattern can include, for example, a back-end-of-line(BEOL) or mid-of-line (MOL) interconnect structure, a front-end-of-line(FEOL) device structure which includes, for example, a high-k metal gatesemiconductor transistor devices, or an alignment mark used foralignment and registration purposes between subsequent fabricationprocessing steps. The alignment mark can generally be fabricated in asacrificial region, or kerf, of a wafer. In some instances the alignmentmark can be adjacent to the device pattern. In the present embodiment,the fabrication of an interconnect structure can be illustratedgenerally on the left side of the structure 100, and the fabrication ofan alignment mark can be illustrated on the right side of the structure100.

It should be noted that FIGS. 1-11 all represent a cross section view ofa wafer having a substrate. The substrate may include a semiconductormaterial or a dielectric material. In the present embodiment, a firstdevice pattern and a second device pattern can be formed in a dielectriclayer using a block first sidewall image transfer technique, describedin detail below. The block first SIT technique can include a blockpatterning technique followed by a device patterning technique. Theinterconnect structure can be formed from the first device pattern andthe alignment mark can be formed from the second device pattern. Boththe first and second device patterns are fabricated concurrently, andsimultaneously undergo the same or similar processing techniques. Itshould be noted that while this description may refer to some componentsof the structure 100 in the singular tense, more than one component maybe depicted throughout the figures and like components are labeled withlike numerals. For example, the specific number of sets of spacersillustrated in the device patterning process is chosen is forillustrative purposes only.

FIG. 1 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process according to oneembodiment. More specifically, the method can start with forming a stackof layers on top of a substrate 102 in which the first and second devicepatterns are to be formed. Again, in the present embodiment, the firstdevice pattern can produce an interconnect structure and the seconddevice pattern can produce an alignment mark, both formed in thesubstrate 102. The stack of layers can include, for example and startingfrom the substrate 102, a tetra-layer hardmask 104, a blockplanarization layer 106, and a block anti-reflective coating layer 108(hereinafter “block ARC” layer), all of which can be formed on top ofone another and in sequence. The tetra-layer hardmask 104 can furtherinclude, for example, a first patterning layer 110, a first hardmasklayer 112, a second patterning layer 114, and a second hardmask layer116 all of which can be formed one top of one another and in sequence.

In one embodiment, the substrate 102 at the bottom of the stack can beany dielectric materials suitable for BEOL or MOL interconnectstructures. In an alternative embodiment the substrate 102 can be anygate materials suitable for FEOL structures. In other embodiments, thesubstrate 102 can be a semiconductor material or a dielectric materialon top of a semiconductor material. The first and second patterninglayers 110, 114 can include silicon oxide and can be formed, forexample, from a tetraethyl orthosilicate (TEOS) precursor to have athickness, in some embodiments, ranging from about 10 nanometers (nm) toabout 100 nm. The first and second hardmask layers 112, 116 can includea metal-nitride, such as titanium-nitride (TiN), boron-nitride (BN), ora metal-oxide and can have a thickness, in some embodiments, rangingfrom about 10 nm to about 70 nm. The first and second hardmask layers112, 114 can preferably, although not necessarily, be formed to have thesame or close to the same thickness to facilitate an etching process asdescribed in more detail below. The block planarization layer 106 can bean organic planarization layer (OPL) or a layer of material that iscapable of being planarized by known chemical mechanical polishingtechniques. In one embodiment, for example, the block planarizationlayer 106 can be an amorphous carbon layer that can be able to withstandthe high process temperatures of subsequent processing steps. The blockplanarization layer 106 can preferably have a thickness ranging fromabout 10 nm to about 300 nm. The block ARC layer 108 can include silicon(Si) and in some embodiments can be referred to as a SiARC layer or abottom anti-reflective coating layer (BARC). The block ARC layer 108 canhave a thickness ranging from about 10 nm to about 100 nm in someembodiments.

With continued reference to FIG. 1, a block pattern 120 can be generatedusing known photolithography and masking techniques. This step, whichcan be referred to as a block litho step or a block patterning step, canbe performed to block or prevent a portion of a subsequently formeddevice patterns from being transferred to the substrate 102 in asubsequent step. During this step, a photo-resist layer 118 can beformed on top of the block ARC layer 108. The photo-resist layer 118 caninclude any suitable photo-resist material. The particular photo-resistmaterial chosen can partly depend upon the desired pattern to be formedand the exposure method used. In one embodiment, the photo-resist layer118 can include a single exposure resist suitable for, for example,argon fluoride (ArF); a double exposure resist suitable for, forexample, thermal cure system; or an extreme ultraviolet (EUV) resistsuitable for, for example, an optical process. In one embodiment, thephoto-resist layer 118 can be formed with a thickness ranging from about30 nm to about 150 nm. The photo-resist layer 118 can then belithographically exposed and developed to create the block pattern 120.The block pattern 120 can be formed by applying any appropriatephoto-exposure method suitable to the type of photo-resist layer beingused, as is well known in the art. The block pattern 120 of the blockpatterning step can define a pattern region 122 of the structure 100.The pattern region 122 can be distinguished from the remainder of thestructure 100, in that a subsequent device patterns can only betransferred to the underlying substrate 102 in the pattern region 122.

FIG. 2 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process, following thestep shown in FIG. 1, according to one embodiment. More specifically,the method can include transferring the block pattern 120 intounderlying layers, for example, the block ARC layer 108 and the blockplanarization layer 106. Transferring of the block pattern 120 in thepresent step can be performed by etching the block ARC layer 108 and theblock planarization layer 106 selective to the second hardmask layer116. A directional etching technique such as a reactive-ion-etchingtechnique can be used to etch the block ARC layer 108 and the blockplanarization layer 106. In one embodiment, the block ARC layer 108 canbe etched with a reactive-ion-etching technique using a fluorocarbonbased etchant, and the block planarization layer 106 can be etched witha reactive-ion-etching technique using an oxygen based etchant. In thepresent step, the photoresist layer 118 can function as a mask duringetching of the block ARC layer 108, and be removed during etching of theblock planarization layer 106. In this instance, the block ARC layer 108can function as a mask during etching of the block planarization layer106. Further, the second hardmask layer 116 can function as an etch-stoplayer during etching of the block planarization layer 106.

FIG. 3 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process, following thestep shown in FIG. 2, according to one embodiment. More specifically,the method can include transferring the block pattern 120 (FIG. 2) intothe second hardmask layer 116. Transferring of the block pattern 120(FIG. 2) in the present step can be performed by etching the secondhardmask layer 116 selective to the second patterning layer 114. Adirectional etching technique such as a reactive-ion-etching techniquecan be used to etch the second hardmask layer 116. In one embodiment,the second hardmask layer 116 can be etched with a reactive-ion-etchingtechnique using a fluorocarbon gas based breakthrough step first, thenfollowed by chlorine based etchant. In the present step, the block ARClayer 108 will be thinned or removed during the breakthrough step, andthe block planarization layer 106 can function as the primary mask foretching of the second hardmask layer 116.

Thereafter, the block planarization layer 106 (FIG. 2) can be removed orlifted off. The block planarization layer 106 (FIG. 2) can be strippedor removed with either a wet clean technique, for example SP clean, orwith a plasma etching technique using an oxygen based plasma. In thepresent embodiment, the block pattern 120 (FIG. 2) is transferred in thepattern region 122 of the structure 100. As described above, the firstand second device patterns will be transferred to the substrate 102 onlyin the pattern region 122. Generally, the substrate 102 will notsubsequently be patterned in any region blocked by the block pattern 120(FIG. 2).

FIG. 4 is a demonstrative illustration of a structure during anintermediate step of a method of forming the first device pattern andthe second device pattern through a block first SIT process, followingthe step shown in FIG. 3, according to one embodiment. Morespecifically, the method can include forming a mandrel 126 above amandrel planarization layer 128 and a mandrel anti-reflective coatinglayer 130 (hereinafter “mandrel ARC layer”). The mandrel planarizationlayer 128 can be substantially similar to the block planarization layer106 (FIG. 2) described in detail above, and the mandrel ARC layer 130can be substantially similar to the block ARC layer 108 (FIG. 2) alsodescribed in detail above.

During this step, a second photo-resist layer 132 can be formed on topof the mandrel ARC layer 130. The second photo-resist layer 132 can besubstantially similar to the first photo-resist layer 118 (FIG. 2)described in detail above. Like above, the particular photo-resistmaterial chosen can partly depend upon the desired pattern to be formedand the exposure method used. The second photo-resist layer 132 can thenbe lithographically exposed and developed to create the mandrel 126. Themandrel 126 can be formed by applying any appropriate photo-exposuremethod suitable to the type of photo-resist layer being used, as is wellknown in the art.

FIG. 5 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process, following thestep shown in FIG. 4, according to one embodiment. More specifically,the method can include depositing a layer of dielectric material 134(hereinafter “dielectric layer”) directly on top of the mandrel ARClayer 130 and the mandrel 126. In one embodiment, the dielectric layer134 can include, for example, silicon nitride or low temperature siliconoxide. The dielectric layer 134 can be deposited with a conformaldeposition technique, using any known atomic layer deposition technique,molecular layer deposition techniques, or future developed depositiontechnique. In one embodiment, the dielectric layer 134 can have asubstantially uniform thickness. In one embodiment, the dielectric layer134 can have a conformal and uniform thickness ranging from about 10 nmto about 50 nm.

In an alternative embodiment, a pattern of the mandrel 126 can belithographically transferred into an underlayer first before depositingthe dielectric layer 134, as described above. Doing so can reduce thetransfer of defects in the mandrel 126 at tight pitches, for exampleless than 22 nm.

FIG. 6 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process, following thestep shown in FIG. 5, according to one embodiment. More specifically,the method can include forming sidewall spacers 136 by subjecting thedielectric layer 134 (FIG. 5) to a directional etching process such as areactive-ion-etching technique. The directional etching process canremove most of the dielectric layer 134 (FIG. 5) from the top of themandrel ARC layer 130 and from the top of the mandrel 126 (FIG. 5). Aportion of the dielectric layer 134 (FIG. 5) can remain along thesidewalls of the mandrel 126 (FIG. 5), forming the sidewall spacers 136.Here, it should be noted that the sidewall spacers 136 depicted in FIG.6 are for illustration purposes and generally can have a slightlydifferent shape from those shown. For example, the sidewall spacers 136can have rounded corners that can be naturally formed during thedirectional etching process as is known in the art. The sidewall spacers136 define a first device pattern 138 and a second device pattern 140which, ultimately can be transferred into the underlying substrate 102.

After directional etching of the dielectric layer 134 (FIG. 5) andformation of the sidewall spacers 136, the mandrel 126 (FIG. 5) can bepulled out or removed. In one embodiment, the mandrel 126 can be removedusing an oxygen-containing plasma in which the sidewall spacers 136won't be trimmed. As described above, and in one embodiment, the firstdevice pattern 138 can represent fabrication of an interconnectstructure, and the second device pattern 140 can represent fabricationof an alignment mark.

FIG. 7 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern and asecond device pattern through a block first SIT process, following thestep shown in FIG. 6, according to one embodiment. More specifically,the method can include transferring the first and second device patterns138, 140 of the sidewall spacers 136, into underlying layers, forexample, the mandrel ARC layer 130 and the mandrel planarization layer128. Transferring of the first and second device patterns 138, 140 inthe present step can be performed by etching the mandrel ARC layer 130and the mandrel planarization layer 128 selective to the second hardmasklayer 116 and the second patterning layer 114. A directional etchingtechnique such as a reactive-ion-etching technique can be used to etchthe mandrel ARC layer 130 and the mandrel planarization layer 128. Inone embodiment, the mandrel ARC layer 130 can be etched with areactive-ion-etching technique using a fluorocarbon based etchant, andthe mandrel planarization layer 128 can be etched with areactive-ion-etching technique using an oxygen based etchant. In thepresent step, the sidewall spacers 136 can function as a mask, and boththe second hardmask layer 116 and the second patterning layer 114 canfunction as etch-stop layers during the etching of the mandrelplanarization layer 128. It should be noted that some portion of thesidewall spacers 136 can be removed during etching of the mandrel ARClayer 130 and the mandrel planarization layer 128. Thus, the sidewallspacers 136 can be shorter in height after etching the mandrel ARC layer130 and the mandrel planarization layer 128.

FIG. 8 is a demonstrative illustration of a structure during anintermediate step of a method of forming the first device pattern 138and the second device 140 pattern through a block first SIT process,following the step shown in FIG. 7, according to one embodiment. Morespecifically, the method can include transferring the first and seconddevice patterns 138, 140 from the mandrel planarization layer 128 to thesecond patterning layer 114. Transferring the first and second devicepatterns 138, 140 in the present step can be performed by etching thesecond patterning layer 114 selective to the first and second hardmasklayers 112, 116. A directional etching technique such as areactive-ion-etching technique can be used to etch the second patterninglayer 114. In one embodiment, the second patterning layer 114 can beetched with a reactive-ion-etching technique using a fluorocarbon basedetchant. In the present step, the mandrel planarization layer 128 canfunction as a mask, and both the first and second hardmask layers 112,116 can function as etch-stop layers during the etching of the secondpatterning layer 114.

More specifically, the second hardmask layer 116 can function as anetch-stop layer and prevent the transfer of the first and second devicepatterns 138, 140 into any region of the structure 100 other than thepattern region 122. Therefore, as a result of the block patterning stepdescribed above and the presence of the second hardmask layer 116, thefirst and second device patterns 138, 140 can only be transferred intothe pattern region 122 of the structure 100.

Furthermore, the sidewall spacers 136 (FIG. 7) and the mandrel ARC layer130 (FIG. 7) can be simultaneously removed during transferring the firstand second device patterns 138, 140 into the second patterning layer114. After transferring the first and second device patterns 138, 140into the second patterning layer 114, the mandrel planarization layer128 can be completely removed using any suitable etching or cleaningtechnique known in the art. In one embodiment, the mandrel planarizationlayer 128 can be removed with an etching technique using an oxygen basedetchant.

FIG. 9 is a demonstrative illustration of a structure during anintermediate step of a method of forming the first device pattern 138and the second device pattern 140 through a block first SIT process,following the step shown in FIG. 8, according to one embodiment. Morespecifically, the method can include transferring the first and seconddevice patterns 138, 140 from the second patterning layer 114 to thefirst hardmask layer 112 selective to the first patterning layer 110Transferring the first and second device patterns 138, 140 in thepresent step can be performed by etching the first hardmask layer 112. Adirectional etching technique such as a reactive-ion-etching techniquecan be used to etch the first hardmask layer 112. In one embodiment, thefirst hardmask layer 112 can be etched with a reactive-ion-etchingtechnique using a fluorocarbon plasma breakthrough step, followed by achlorine based etchant. In the present step, the second patterning layer114 can function as a mask, and the first patterning layer 110 canfunction as an etch-stop layer during the etching of the first hardmask112. Furthermore, the second hardmask layer 116 (FIG. 8) can besimultaneously removed during transferring the first and second devicepatterns 138, 140 into the first hardmask layer 112.

FIG. 10 is a demonstrative illustration of a structure during anintermediate step of a method of forming a first device pattern 138 anda second device pattern 140 through a block first SIT process, followingthe step shown in FIG. 9, according to one embodiment. Morespecifically, the method can include transferring the first and seconddevice patterns 138, 140 from the first hardmask 112 (FIG. 9) to thesubstrate 102. Transferring the first and second device patterns 138,140 in the present step can be performed by etching the first patterninglayer 110 and the substrate 102 to a desired depth. The desired depthcan depend on the ultimate function of the structure 100. A directionaletching technique such as a reactive-ion-etching technique can be usedto etch the first patterning layer 110 and the substrate 102. In oneembodiment, the first patterning layer 110 and the substrate 102 can beetched with a reactive-ion-etching technique using a fluorocarbon basedetchant. In the present step, the first hardmask layer 112 (FIG. 9) canfunction as a mask, and can have a high etch-selectivity relative to thefirst patterning layer 110 and the substrate 102. Furthermore, the firsthardmask layer 112 (FIG. 9) and the first patterning layer 110 can beremoved in subsequent steps using any suitable removal technique knownin the art.

FIG. 11 is a demonstrative illustration of a final structure of a methodof forming a first device pattern 138 and a second device pattern 140through a block first SIT process, following the step shown in FIG. 10,according to one embodiment. More specifically, the final structure caninclude an interconnect structure 142 and an alignment mark 144 formedby filling the first device pattern 138 and the second device pattern140 with a conductive interconnect material. In one embodiment, typicalprocessing techniques known in the art can be used to fill the first andsecond device patterns 138, 140 with a conductive interconnect materialto form the interconnect structure 142 and the alignment mark 144. Itshould be noted that the method of forming a first device pattern 138and a second device pattern 140 through a block first SIT process is notlimited to the formation of an interconnect structure and an alignmentmark. In one embodiment, one or more fins may be formed in asemiconductor material in order to fabricate a fin field effecttransistor device.

The above described block first SIT technique can have distinctadvantages over other comparable techniques. The process window of theblock first SIT technique described above is not artificially restrictedby the height of the sidewall spacers 136 because the second hardmasklayer 116 prevents the sidewall spacers 136 outside the pattern region122 from being transferred to the underlying substrate 102.Additionally, the block first SIT technique can produce a solidalignment mark, as opposed to segmented or hollow alignment marksgenerally produced during comparable SIT transfer techniques. The solidalignment mark offers higher contrast allowing for improved alignmentbetween processing steps.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method comprising: forming a tetra-layerhardmask above a substrate, the tetra-layer hardmask comprising a secondhardmask layer above a first hardmask layer; removing a portion of thesecond hardmask layer of the tetra-layer hardmask within a patternregion of a structure comprising the substrate and the tetra-layerhardmask; forming a set of sidewall spacers above the tetra-layerhardmask defining a device pattern; and transferring a portion of thedevice pattern into the substrate within the pattern region of thestructure.
 2. The method of claim 1, wherein forming the set of sidewallspacers above the tetra-layer hardmask defining the device patterncomprises: creating a mandrel, lithographically, from a photo-resistmaterial; depositing a conformal layer of dielectric material coveringthe mandrel; performing a directional etch of the conformal layer ofdielectric material forming the set of sidewall spacers; and removingthe mandrel.
 3. The method of claim 1, wherein transferring the portionof the device pattern into the substrate within the pattern region ofthe structure comprises: transferring the portion of the device patterninto the first hardmask layer within the pattern region of thestructure; and transferring the portion of the device pattern from thefirst hardmask layer into the substrate within the pattern region of thestructure.
 4. The method of claim 3, wherein transferring the portion ofthe device pattern into the first hardmask layer within the patternregion of the structure comprises: transferring the portion of thedevice pattern into a mandrel planarization layer above the tetra-layerhardmask; and transferring the portion of the device pattern from themandrel planarization layer into the first hardmask layer.
 5. The methodof claim 1, wherein forming the tetra-layer hardmask above the substratecomprises: forming a first patterning layer directly above thesubstrate; forming the first hardmask layer directly above the firstpatterning layer; forming a second patterning layer directly above thefirst hardmask layer; and forming the second hardmask layer directlyabove the second patterning layer.
 6. The method of claim 1, furthercomprising: depositing a metal within the device pattern transferredinto the substrate.
 7. A method comprising: forming a tetra-layerhardmask comprising a second hardmask layer above a first hardmasklayer; defining a pattern region in the second hardmask layer; forming adevice pattern above the tetra-layer hardmask; and transferring thedevice pattern into a substrate below the tetra-layer hardmask, whereinthe device pattern is transferred into the substrate only in the patternregion defined by the second hardmask layer.
 8. The method of claim 7,wherein defining the pattern region is accomplished using a lithographicmasking and etching technique.
 9. The method of claim 7, wherein forminga device pattern above the tetra-layer hardmask comprises: creating amandrel, lithographically, from a photo-resist material; depositing aconformal layer of dielectric material covering the mandrel; performinga directional etch of the conformal layer of dielectric material forminga set of sidewall spacers; and removing the mandrel.
 10. The method ofclaim 7, wherein forming the device pattern above the tetra-layerhardmask comprises: forming a first device pattern intended to fabricatean interconnect structure; and forming a second device pattern intendedto fabricate an alignment mark.
 11. The method of claim 7, whereintransferring the device pattern is accomplished using a sidewall imagetransfer technique.
 12. The method of claim 7, wherein transferring thedevice pattern into the substrate below the tetra-layer hardmaskcomprises: transferring the device pattern into a mandrel ARC layerabove a mandrel planarization layer above the tetra-layer hardmask; andtransferring the device pattern from the mandrel ARC layer into themandrel planarization layer; transferring the device pattern from themandrel planarization layer into the first hardmask layer; andtransferring the device pattern from the first hardmask layer into thesubstrate.
 13. The method of claim 7, wherein forming the tetra-layerhardmask comprises: forming a first patterning layer directly above thesubstrate; forming the first hardmask layer directly above the firstpatterning layer; forming a second patterning layer directly above thefirst hardmask layer; and forming the second hardmask layer directlyabove the second patterning layer.
 14. A method comprising: forming atetra-layer hardmask above a substrate, the tetra-layer hardmaskcomprising a first patterning layer, a first hardmask layer, a secondpatterning layer, and a second hardmask layer all of which are formedone top of one another and in sequence; forming a block pattern from afirst photo-resist material above the tetra-layer hardmask; transferringthe block pattern from the first photo-resist material into the secondhardmask layer, wherein the block pattern in the second hardmask layerdefines a pattern region; forming a device pattern using a set ofsidewall spacers above the second hardmask layer; transferring thedevice pattern into the first hardmask layer, only within the patternregion; and transferring the device pattern into the substrate, onlywithin the pattern region.
 15. The method of claim 14, wherein formingthe device pattern using the set of sidewall spacers above the secondhardmask layer comprises: creating a mandrel, lithographically, from asecond photo-resist layer; depositing a conformal layer of dielectricmaterial covering the mandrel; performing a directional etch of theconformal layer of dielectric material forming the set of sidewallspacers; and removing the mandrel.
 16. The method of claim 14, whereinforming the device pattern using the set of sidewall spacers above thesecond hardmask layer comprises: forming a first device pattern intendedto fabricate an interconnect structure; and forming a second devicepattern intended to fabricate an alignment mark.
 17. The method of claim14, wherein transferring the device pattern into the first hardmasklayer comprises: transferring the device pattern into a mandrel ARClayer above a mandrel planarization layer above the tetra-layerhardmask; and transferring the device pattern from the mandrel ARC layerinto the mandrel planarization layer; and transferring the devicepattern from the mandrel planarization layer into the first hardmasklayer.